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Section 9 Bus State Controller
Page 232 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
9.2 Input/Output Pins
Table 9.1 shows the pin configuration.
Table 9.1 Pin Configuration
Name I/O Function
A25 to A0 Output Address bus
D15 to D0 I/O Data bus
BS Output Bus cycle start
CS0 to CS4 Output Chip select
CS5/CE1A, CS6/CE1B Output Chip select
Function as PCMCIA card select signals for D7 to D0 when
PCMCIA is used.
CE2A, CE2B Output Function as PCMCIA card select signals for D15 to D8.
RD/WR Output Read/write
Connects to WE pins when SDRAM or SRAM with byte
selection is connected.
RD Output Read pulse signal (read data output enable signal)
Functions as a strobe signal for indicating memory read
cycles when PCMCIA is used.
ICIOWR/AH Output Functions as a strobe signal for indicating I/O write cycles
when PCMCIA is used.
Functions as the address hold signal when the MPX-I/O is
used.
ICIORD Output Functions as a strobe signal for indicating I/O read cycles
when PCMCIA is used.
WE1/DQMU/WE Output Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a SRAM with byte
selection is connected.
Functions as the select signals for D15 to D8 when SDRAM
is connected.
Functions as a strobe signal for indicating memory write
cycles when PCMCIA is used.