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Section 19 Serial I/O with FIFO
Page 954 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
0 RFOVF 0 R/W Receive FIFO Overflow
0: No receive FIFO overflow
1: Receive FIFO overflow
A receive FIFO overflow means that writing has occurred
due to reception operation when the receive FIFO is full.
When an overflow of the receive FIFO occurs, the receive
data which caused the overflow is lost.
When this bit is set to 1, it is cleared to 0 by this
module. Writing 0 to this bit is invalid.