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Section 11 Multi-Function Timer Pulse Unit 2
R01UH0134EJ0400 Rev. 4.00 Page 445 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
11.3.2 Timer Mode Register (TMDR)
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of
each channel. This module has five TMDR registers, one each for channels 0 to 4. TMDR register
settings should be changed only when TCNT operation is stopped.
Bit:
Initial value:
R/W:
7654321
0
00000000
R R/W R/W R/W R/W R/W R/W R/W
- BFE BFB BFA MD[3:0]
Bit Bit Name
Initial
Value R/W Description
7 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
6 BFE 0 R/W Buffer Operation E
Specifies whether TGRE_0 and TGRF_0 are to operate
in the normal way or to be used together for buffer
operation.
TGRF compare match is generated when TGRF is
used as the buffer register.
In channels 1 to 4, this bit is reserved. It is always read
as 0 and the write value should always be 0.
0: TGRE_0 and TGRF_0 operate normally
1: TGRE_0 and TGRF_0 used together for buffer
operation