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Section 21 IEBus
TM
Controller
Page 1102 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
21.3 Register Descriptions
Table 21.8 shows the register configuration.
Table 21.8 Register Configuration
Register Name Abbreviation R/W
Initial
Value Address
Access
Size
IEBus control register IECTR R/W H'00 H'FFFE F000 8
IEBus command register IECMR W H'00 H'FFFE F001 8
IEBus master control register IEMCR R/W H'00 H'FFFE F002 8
IEBus master unit address
register 1
IEAR1 R/W H'00 H'FFFE F003 8
IEBus master unit address
register 2
IEAR2 R/W H'00 H'FFFE F004 8
IEBus slave address setting
register 1
IESA1 R/W H'00 H'FFFE F005 8
IEBus slave address setting
register 2
IESA2 R/W H'00 H'FFFE F006 8
IEBus transmit message length
register
IETBFL R/W H'00 H'FFFE F007 8
IEBus reception master address
register 1
IEMA1 R H'00 H'FFFE F009 8
IEBus reception master address
register 2
IEMA2 R H'00 H'FFFE F00A 8
IEBus receive control field register IERCTL R H'00 H'FFFE F00B 8
IEBus receive message length
register
IERBFL R H'00 H'FFFE F00C 8
IEBus lock address register 1 IELA1 R H'00 H'FFFE F00E 8
IEBus lock address register 2 IELA2 R H'00 H'FFFE F00F 8
IEBus general flag register IEFLG R H'00 H'FFFE F010 8
IEBus transmit status register IETSR R/(W)* H'00 H'FFFE F011 8
IEBus transmit interrupt enable
register
IEIET R/W H'00 H'FFFE F012 8
IEBus receive status register IERSR R/(W)* H'00 H'FFFE F014 8