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Section 36 List of Registers
Page 1862 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Module Name Register Name Abbreviation
Number
of Bits Address
Access
Size
Controller area
network
Mailbox Interrupt Mask Register 1_0 MBIMR1_0 16 H'FFFE5050 16
Mailbox Interrupt Mask Register 0_0 MBIMR0_0 16 H'FFFE5052 16
Unread Message Status Register 1_0 UMSR1_0 16 H'FFFE5058 16
Unread Message Status Register 0_0 UMSR0_0 16 H'FFFE505A 16
Timer Trigger Control Register 0_0 TTCR0_0 16 H'FFFE5080 16
Cycle Maximum/Tx-Enable Window
Register_0
CMAX_TEW_0 16 H'FFFE5084 16
Reference Trigger Offset Register_0 RFTROFF_0 16 H'FFFE5086 16
Timer Status Register_0 TSR_0 16 H'FFFE5088 16
Cycle Counter Register_0 CCR_0 16 H'FFFE508A 16
Timer Counter Register_0 TCNTR_0 16 H'FFFE508C 16
Cycle Time Register_0 CYCTR_0 16 H'FFFE5090 16
Reference Mark Register_0 RFMK_0 16 H'FFFE5094 16
Timer Compare Match Register 0_0 TCMR0_0 16 H'FFFE5098 16
Timer Compare Match Register 1_0 TCMR1_0 16 H'FFFE509C 16
Timer Compare Match Register 2_0 TCMR2_0 16 H'FFFE50A0 16
Tx-Trigger Time Selection Register_0 TTTSEL_0 16 H'FFFE50A4 16
Mailbox n Control 0_H_0
(n = 0 to 31)
MBn_
CONTROL0_H_0
(n = 0 to 31)
16 H'FFFE5100
+ n × 32
16, 32
Mailbox n Control 0_L_0
(n = 0 to 31)
MBn_
CONTROL0_L_0
(n = 0 to 31)
16 H'FFFE5102
+ n × 32
16
Mailbox n Local Acceptance Filter Mask
0_0 (n = 0 to 31)
MBn_LAFM0_0
(n = 0 to 31)
16 H'FFFE5104
+ n × 32
16, 32
Mailbox n Local Acceptance Filter Mask
1_0 (n = 0 to 31)
MBn_LAFM1_0
(n = 0 to 31)
16 H'FFFE5106
+ n × 32
16
Mailbox n Data 01_0 (n = 0 to 31) MBn_
DATA_01_0
(n = 0 to 31)
16 H'FFFE5108
+ n × 32
8, 16, 32