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Section 25 NAND Flash Memory Controller
R01UH0134EJ0400 Rev. 4.00 Page 1295 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
17 QTSEL 0 R/W Select Dividing Rates for Flash Clock
Selects the dividing rate of clock FCLK in the flash
memory.
0: Divides a clock (P) provided from the clock pulse
generator by two and uses it as FCLK.
1: Divides a clock (P) provided from the clock pulse
generator by four and uses it as FCLK.
16 to 14 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
13, 12 ECCPOS
[1:0]
00 R/W ECC Embedding Position Specification
ECCPOS[2:0] (bits 25, 13, and 12 of this register)
specifies the position to place ECC in the control code
field when 3- or 4-symbol ECC circuit is used
When 4ECCEN = 0 (ECC is eight bytes)
000: Places ECC with offset of 512 bytes in a sector
001: Places ECC with offset of 516 bytes in a sector
010: Places ECC with offset of 520 bytes in a sector
Other than above: Setting prohibited
When 4ECCEN = 1 (ECC is ten bytes)
000: Places ECC with offset of 518 bytes in a sector
001: Places ECC with offset of 517 bytes in a sector
010: Places ECC with offset of 516 bytes in a sector
011: Places ECC with offset of 515 bytes in a sector
100: Places ECC with offset of 514 bytes in a sector
101: Places ECC with offset of 513 bytes in a sector
110: Places ECC with offset of 512 bytes in a sector
111: Setting prohibited