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Section 37 Electrical Characteristics
Page 1992 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Tc1Tr T cw Td1 Tde
t
AD1
t
AD1
t
CSD1
t
AD1
t
RWD1
t
RWD1
t
CSD1
t
AD1
t
AD1
t
AD1
t
RDH2
t
RDS2
t
RASD1
t
RASD1
Row address
READA command
Column address
t
CASD1
t
CASD1
t
BSD
t
BSD
(High)
t
DQMD1
t
DQMD1
t
DACD
t
DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
CKIO
A25 to A0
CSn
RD/WR
A12/A11
*
1
D15 to D0
RAS
CAS
BS
CKE
DQMxx
DACKn
TENDn*
2
Figure 37.17 Synchronous DRAM Single Read Bus Cycle
(Auto Precharge, CAS Latency 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)