Section 11 Multi-Function Timer Pulse Unit 2
Page 568 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
(o) Counter Clearing by TGRA_3 Compare Match
In complementary PWM mode, by setting the CCE bit in the timer waveform control register
(TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare
match.
Figure 11.62 illustrates an operation example.
Notes: 1. Use this function only in complementary PWM mode 1 (transfer at crest)
2. Do not specify synchronous clearing by another channel (do not set the SYNC0 to
SYNC4 bits in the timer synchronous register (TSYR) to 1).
3. Do not set the PWM duty value to H'0000.
4. Do not set the PSYE bit in timer output control register 1 (TOCR1) to 1.
TGRA_3
TGRB_3
TCDR
TDDR
H'0000
Output waveform
Output waveform
Output waveform is active-high.
Counter cleared
by TGRA_3 compare match
Figure 11.62 Example of Counter Clearing Operation by TGRA_3 Compare Match