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Section 28 Sampling Rate Converter
Page 1648 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
11 UDEN 0 R/W Output Data FIFO Underflow Interrupt Enable
Enables/disables the output data FIFO underflow
interrupt to be generated when output data FIFO is
read and the UDF bit in SRCSTAT is set to 1 while
the number of data units in the output data FIFO is
zero.
0: Disables output data FIFO underflow interrupt
requests.
1: Enables output data FIFO underflow interrupt
requests.
10 OVEN 0 R/W Output Data FIFO Overwrite Interrupt Enable
Enables/disables the output data FIFO overwrite
interrupt request to be issued when the conversion for
the next data has been completed while the number
of data units in the output FIFO is eight, thus setting
the OVF bit in the status register (SRCSTAT) to 1.
When OVEN = 1: Conversion processing is stopped
until the OVF bit is cleared by the CPU accessing to
SRCSTAT when the output data FIFO overwrite
interrupt is generated. At this time, conversion result
writing to the output data FIFO is also stopped.
OVEN = 0: The OVF bit is automatically cleared when
the output data FIFO has space, and conversion
processing can be continued.
0: Output data FIFO overwrite interrupt is disabled.
1: Output data FIFO overwrite interrupt is enabled.
9 FL 0 R/W Internal Work Memory Flush
Writing 1 to this bit starts converting the sampling rate
of all the data in the input FIFO, input buffer memory,
and intermediate memory (i.e., flush processing). This
bit is always read as 0. When SRCEN = 0, writing 1 to
this bit does not trigger flush processing.
In addition, when 1 is written to the FL bit while the
number of data units in the input buffer memory is
less than the values shown in tables 28.9 and 28.10,
valid output data cannot be received. Thus the
internal work memory is cleared without triggering the
flush processing.