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Section 27 Video Display Controller 3
Page 1602 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.22 Graphics Image Start Position Registers (GROPDPHV1 and GROPDPHV2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
------
-
GROPDPV[9:0]
- - - - - GROPDPH[9:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value R/W Description
31 to 26 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
25 to 16 GROPDPV
[9:0]
H'000 R/W These bits specify the vertical display start position
of the graphics image area in number of lines.
15 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0 GROPDPH
[9:0]
H'000 R/W These bits specify the horizontal display start
position of the graphics image area in number of
pixels.
Note: The display start address is offset as follows (see figure 27.19).
Vertical offset: (GROPDPV value) + 1 line
Horizontal offset: (GROPDPH value) + 16 pixels