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Section 18 Serial Sound Interface
Page 930 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
18.4.4 Transmit Operation
Transmission can be controlled either by DMA transfer or interrupt.
DMA control is preferred to reduce the processor load. In DMA control mode, the processor will
only receive interrupts if there is an underflow or overflow of data or if the DMA transfer has been
completed.
The alternative method is using the interrupts that this module generates to supply data as
required.
When disabling this module, the clock* must be kept supplied to this module until the IIRQ bit
indicates that the module is in the idle state.
Figure 18.20 shows the transmit operation in DMA control mode, and figure 18.21 shows the
transmit operation in interrupt control mode.
Note: * Input clock from the SSISCK pin when SCKD = 0.
Oversampling clock when SCKD = 1.