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Section 18 Serial Sound Interface
R01UH0134EJ0400 Rev. 4.00 Page 907 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
28 TOIRQ 0 R/(W)* Transmit Overflow Error Interrupt Status Flag
This status flag indicates that transmit data was
supplied at a higher rate than was required.
This bit is set to 1 regardless of the value of the TOIEN
bit and can be cleared by writing 0 to this bit.
If TOIRQ = 1 and TOIEN = 1, an interrupt occurs.
If TOIRQ = 1, SSIFTDR had data written to it while the
transmit FIFO is full (TDC = H'8). This will lead to the
loss of data and a potential corruption of multi-channel
data.
27 RUIRQ 0 R/(W)* Receive Underflow Error Interrupt Status Flag
This status flag indicates that receive data was supplied
at a lower rate than was required.
This bit is set to 1 regardless of the value of the RUIEN
bit and can be cleared by writing 0 to this bit.
If RUIRQ = 1 and RUIEN = 1, an interrupt occurs.
If RUIRQ = 1, SSIFRDR was read while the receive
FIFO is empty (RDC = H'0).This can cause invalid
receive data to be stored, which may lead to corruption
of multi-channel data.
26 ROIRQ 0 R/(W)* Receive Overflow Error Interrupt Status Flag
This status flag indicates that receive data was supplied
at a higher rate than was required.
This bit is set to 1 regardless of the value of the ROIEN
bit and can be cleared by writing 0 to this bit.
If ROIRQ = 1 and ROIEN = 1, an interrupt occurs.
If ROIRQ = 1, SSIRDR was not read before there was
new unread data written to it. This will lead to the loss
of data and a potential corruption of multi-channel data.
Note: When an overflow error occurs, the current data
in the data buffer of this module is overwritten by
the next incoming data from the SSI interface.