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Section 10 Direct Memory Access Controller
R01UH0134EJ0400 Rev. 4.00 Page 425 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. However, in the case of internal module request, along with the exception of
the multi-function timer pulse unit 2 and the compare match timer as the transfer
request source, the requesting module must be designated as the transfer source or the
transfer destination.
2. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
3. If the transfer request is an external request, channels 0 and 1 are only available (Only
channel 0 in the SH7262 Group).
4. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the compare
match timer and the multi-function timer pulse unit 2 are only available.
5. In the case of on-chip peripheral module request, only cycle steal except for the
CD-ROM decoder, the multi-function timer pulse unit 2, and the compare match timer
as the transfer request source.
6. Channel 0 is only available in the SH7262 Group.
(4) Bus Mode and Channel Priority
In priority fixed mode (CH0 > CH1), when channel 1 is transferring data in burst mode and a
request arrives for transfer on channel 0, which has higher-priority, the data transfer on channel 0
will begin immediately. In this case, if the transfer on channel 0 is also in burst mode, the transfer
on channel 1 will only resume on completion of the transfer on channel 0.
When channel 0 is in cycle steal mode, one transfer-unit of data on this channel, which has the
higher priority, is transferred. Data is then transferred continuously to channel 1 without releasing
the bus. The bus mastership will then switch between the two in this order: channel 0, channel 1,
channel 0, channel 1, etc. That is, the CPU cycle after the data transfer in cycle steal mode is
replaced with a burst-mode transfer cycle (priority execution of burst-mode cycle). An example of
this is shown in figure 10.10.
When multiple channels are in burst mode, data transfer on the channel that has the highest
priority is given precedence. When DMA transfer is being performed on multiple channels, the
bus mastership is not released to another bus-master device until all of the competing burst-mode
transfers have been completed.