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Section 25 NAND Flash Memory Controller
Page 1318 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
9 to 0 PATn[9:0] Undefined R nth Error Correction Pattern Indication
Indicates the pattern for the correction of the nth error of
the four errors.
Patterns for which PAT[9:8] = B'11 and patterns for
which all bits of PAT[9:0] are 0 are invalid (and indicate
that generation of an error pattern was not possible or
that there were no errors).
The initial value is H'3FF.
The values of these bits that are set after the
4ECCEND bit in the 4-symbol ECC control register is
set to 1 are valid. Note that starting to read out the data
for the next sector before reading these bits will destroy
the data.
Note: n = 1 to 4
25.3.16 4-Symbol ECC Control Register (FL4ECCCR)
FL4ECCCR is a 32-bit readable register that indicates the processing states of the 4-symbol ECC
circuit. This register consists of flag bits to which only 0 can be written. To clear a flag, write 0 to
the target flag bit and 1 to the other flag bits.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
151413121110987654321
0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRRRRRRRRR/(W)*R/(W)*R/(W)*
------
----
----------
-- -----
--
4ECC
FA
4ECC
END
4ECC
EXST
Bit Bit Name
Initial
Value R/W Description
31 to 3 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.