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Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00 Page 295 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 16 bits are always
read in case of a 16-bit device. When writing, only the WEn signal for the byte to be written is
asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer with this signal, to avoid
output collision.
Figures 9.4 and 9.5 show the basic timings in continuous access to normal space. If the WM bit in
CSnWCR is cleared to 0, a Tnop cycle is inserted after the CSn space access to evaluate the
external wait (figure 9.4). If the WM bit in CSnWCR is set to 1, external waits are ignored and no
Tnop cycle is inserted (figure 9.5).
CKIO
A25 to A0
RD
RD/WR
D15 to D0
WEn
D15 to D0
DACKn
BS
WAIT
CSn
T1 T2 Tnop T1 T2
Read
Write
*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4 Continuous Access to Normal Space (1)
Bus Width = 16 Bits, Longword Access, CSnWCR.WM Bit = 0
(Access Wait = 0, Cycle Wait = 0)