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Section 22 Renesas SPDIF Interface
Page 1164 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
3 CSRX 0 R Channel 1 and Channel 2 Status for Receiver
Indicates the status of the receiver channel status
registers. This bit is cleared by reading from the receiver
channel status registers. If bit RCSI in the control register
is set this causes an interrupt.
0: Receiver channel status registers are empty
1: Receiver channel status registers are full
2 CBRX 0 R Channel 1 and Channel 2 Buffers for Receiver
Indicates the status of the receiver audio channel
registers. This bit is cleared by reading from the receiver
audio channel registers. If bit RCBI in the control register
is set this causes an interrupt.
0: Receiver audio channel registers are empty
1: Receiver audio channel registers are full
1 CSTX 0 R Channel 1 and Channel 2 Status for Transmitter
Indicates the status of the transmitter channel status
registers. This bit is cleared by writing to the transmitter
channel status registers. If bit TCSI in the control register
is set this causes an interrupt.
0: Transmitter channel status register is full
1: Transmitter channel status register is empty
0 CBTX 0 R Channel 1 and Channel 2 Buffers for Transmitter
Indicates the status of the transmitter audio channel
registers. This bit is cleared by writing to the transmitter
audio channel registers. If bit TCBI in the control register
is set this causes an interrupt.
0: Transmitter audio channel registers are full
1: Transmitter audio channel registers are empty
Note: * When an error bit is detected during DMA transfer, DMA transfer settings must be made
again. In this case, the Renesas SPDIF's module enable bit (either the RME or TME bit)
and the DMA enable bit (either the RDE or TDE bit) must be disabled and the error
status must be cleared before making DMA transfer settings again. Then the module
enable bit should be set and DMA transfer can be started again.