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Section 24 A/D Converter
Page 1264 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
24.3.2 A/D Control/Status Register (ADCSR)
ADCSR is a 16-bit readable/writable register that selects the mode, controls the A/D converter,
and enables or disables starting of A/D conversion by external trigger input.
1514131211109876543210
Bit:
Initial value:
R/W:
0000000000000000
R/(W)*
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: Only 0 can be written to clear the flag after 1 is read.*1
ADF ADIE ADST TRGS[3:0] CKS[2:0] MDS[2:0] CH[2:0]
Bit Bit Name
Initial
Value R/W Description
15 ADF 0 R/(W)*
1
A/D End Flag
Status flag indicating the end of A/D conversion.
[Clearing conditions]
Cleared by reading ADF while ADF = 1, then
writing 0 to ADF
Cleared when the direct memory access controller
is activated by ADI interrupt and ADDR is read
[Setting conditions]
A/D conversion ends in single mode
A/D conversion ends for the selected channels in
multi mode
A/D conversion ends for the selected channels in
scan mode
14 ADIE 0 R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at
the end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled