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Section 37 Electrical Characteristics
Page 1988 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Ta 1 Ta 2 Ta 3 T1 Tw Twx T2
t
AD1
t
CSD1
t
AD1
t
RWD1
t
RWD1
t
CSD1
t
RSD
t
RSD
t
RDS1
t
WED1
t
WED1
Data
Data
t
BSD
t
BSD
t
WTH
t
WTS
t
AHD
t
AVVH
t
AVVH
t
AHD
t
WTH
t
WTS
t
DACD
t
DACD
Address
t
WDD1
t
MAD
CKIO
A25 to A0
CS5
RD/WR
RD
AH
D15 to D0
Read
WE1, WE0
BS
WAIT
DACKn*
Note: * The waveform for DACKn and TENDn is when active low is specified.
D15 to D0
Write
Address
t
MAH
t
MAD
t
AHD
t
DACD
t
DACD
TENDn*
t
MAH
t
WDH1
t
WDH4
t
RDH1
Figure 37.13 MPX-I/O Interface Bus Cycle
(Three Address Cycles, One Software Wait Cycle, One External Wait Cycle)