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Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00 Page 1649 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
8 CL 0 R/W Internal Work Memory Clear
Writing 1 to this bit clears the input FIFO, output
FIFO, input buffer memory, intermediate memory, and
accumulator. This bit is always read as 0. Even when
SRCEN = 0, writing 1 to this bit clears the processing.
7 to 4 IFS[3:0] All 0 R/W Input Sampling Rate
Specifies the input sampling rate.
0000: 8.0 kHz
0001: 11.025 kHz
0010: 12.0 kHz
0011: Setting prohibited
0100: 16.0 kHz
0101: 22.05 kHz
0110: 24.0 kHz
0111: Setting prohibited
1000: 32.0 kHz
1001: 44.1 kHz
1010: 48.0 kHz
1011: Setting prohibited
1100: Setting prohibited
1101: Setting prohibited
1110: Setting prohibited
1111: Setting prohibited
Note: For channel 1, these bits are reserved and
always read as 0. The write value should
always be 0.
3 to 1 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.