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Section 21 IEBus
TM
Controller
R01UH0134EJ0400 Rev. 4.00 Page 1133 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
21.3.20 IEBus Clock Selection Register (IECKSR)
IECKSR is a readable/writable 8-bit register that specifies the clock used in this module.
76543210
00000001
R R R R/W R R/W R/W R/W
Bit:
Initial value:
R/W:
- - - CKS3 - CKS[2:0]
Bit Bit Name
Initial
Value
R/W Description
7 to 5 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
4 CKS3 0 R/W Input Clock Selection 3*
1
*
2
Specifies the clock for this module
0: Peripheral clock (P)
1: AUDIO_X1, AUDIO_X2
3 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
2 to 0 CKS[2:0] 001 R/W Input Clock Selection 2 to 0*
1
Specifies the division ratio of the clock for this module
000: Setting prohibited
001: This module uses the 1/2 divided clock of IEB
specified by CKS3 (IEB 12 MHz, 12.58 MHz).
010: This module uses the 1/3 divided clock of IEB
specified by CKS3 (IEB 18 MHz, 18.87 MHz).
011: This module uses the 1/4 divided clock of IEB
specified by CKS3 (IEB 24 MHz, 25.16 MHz).
100: This module uses the 1/5 divided clock of IEB
specified by CKS3 (IEB 30 MHz, 31.45 MHz).
101: This module uses the 1/6 divided clock of IEB
specified by CKS3 (IEB 36 MHz).
110: Setting prohibited
111: Setting prohibited
Notes: 1. Do not change the setting of CKS3 and CKS[2:0] while IEBus is in transmit/receive
operation.
2. When the CKS3 bit is set to 1, be sure to set the MSTP36 bit in STBCR3 to 0. For the
setting of STBCR3, see section 33, Power-Down Modes.