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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 149 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.6.4 General Illegal Instructions
When an undefined code, including FPU instructions and FPU-related CPU instructions in FPU
module standby state, placed anywhere other than immediately after a delayed branch instruction,
i.e., in a delay slot, is decoded, general illegal instruction exception handling starts. When the FPU
has entered a module standby state, the floating point instruction and FPU-related CPU
instructions are handled as undefined codes. If these instructions are placed anywhere other than
immediately after a delayed branch instruction (i.e., in a delay slot) and then decoded, general
illegal instruction exception handling starts.
In general illegal instruction exception handling, the CPU handles general illegal instructions in
the same way as slot illegal instructions. Unlike processing of slot illegal instructions, however,
the program counter value stored is the start address of the undefined code.
6.6.5 Integer Division Exceptions
When an integer division instruction performs division by zero or the result of integer division
overflows, integer division instruction exception handling starts. The instructions that may become
the source of division-by-zero exception are DIVU and DIVS. The only source instruction of
overflow exception is DIVS, and overflow exception occurs only when the negative maximum
value is divided by 1. The CPU operates as follows:
1. The exception service routine start address which corresponds to the integer division exception
that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
integer division instruction at which the exception occurred.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. The jump that occurs is not a delayed branch.