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Section 21 IEBus
TM
Controller
R01UH0134EJ0400 Rev. 4.00 Page 1127 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
21.3.18 IEBus Receive Status Register (IERSR)
IERSR detects receive busy, receive start, receive normal completion, or receive completion with
an error. Each status flag in IERSR corresponds to a bit in the IEIER that enables/disables each
interrupt. This register is cleared by writing 1 to each bit.
76543210
00000000
R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*R/(W)*
Bit:
Initial value:
R/W:
RXBSY RXS RXF RXEDE RXEOVE
RXE
RTME
RXEDLE RXEPE
Bit Bit Name
Initial
Value R/W Description
7 RXBSY 0 R/(W)* Receive Busy
Indicates that the receive data is stored in the receive
data buffer (IERB001 to IERB128). Clear this bit after
reading out all data. The next receive data cannot be
received while this bit is set.
[Setting condition]
When all receive data has been written to the
receive data buffer.
[Clearing condition]
When 1 is written
6 RXS 0 R/(W)* Receive Start Detection
Indicates that this module starts reception.
[Setting condition]
When the data from the master unit to message
length field has been received correctly in slave
reception
[Clearing condition]
When 1 is written