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Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00 Page 833 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
16.4.8 SPI Operation
(1) Multi-Master Mode Operation
This section explains the operation in multi-master mode.
(a) Starting Serial Transfer
A serial transfer is started when transmit data is copied from the transmit buffer to the shift
register, the shift register becomes full, and the receive buffer has a space for the receive data
length. If transmit data has already been written to the shift register, data is not copied from the
transmit buffer to the shift register.
For details of the transfer format, see section 16.4.4, Transfer Format.
(b) Terminating Serial Transfer
Irrespective of the CPHA bit in the command register (SPCMD), this module terminates the serial
transfer after transmitting an RSPCK edge corresponding to the final sampling timing. After the
serial transfer is completed, receive data is copied from the shift register to the receive buffer. If
the receive buffer does not have a space for the receive data length after receive data is copied
from the shift register to the receive buffer, another serial transfer will not be performed. In order
to perform another serial transfer, data for the receive data length should be read from the receive
buffer to secure the space for the receive data.
It should be noted that the final sampling timing varies depending on the bit length of transfer
data. In master mode, the data length depends on the settings in bits SPB3 to SPB0 in SPCMD.
For details on the transfer format, see section 16.4.4, Transfer Format.