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Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00 Page 1047 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit 0 — Timer Overrun/Next_is_Gap Reception/Message Error (TSR0): This flag is assigned
to three different functions. It indicates that the Timer has overrun when working in event-trigger
mode, time reference message with Next_is_Gap set has been received in time-trigger mode, and
error detected on the CAN bus has occurred in test mode, respectively. Test mode has higher
priority with respect to the other settings.
Bit0: TSR0 Description
0 Timer (TCNTR) has not overrun in event-trigger mode (Initial value)
Time reference message with Next_is_Gap has not been received in time-
trigger mode message error has not occurred in test mode.
[Clearing condition] Writing '1' to IRR13
1 [Setting condition]
Timer (TCNTR) has overrun and changed from H'FFFF to H'0000 in event-
trigger mode.time reference message with Next_is_Gap has been received
in time-trigger mode message error has occurred in test mode
(5) Cycle Counter Register (CCR)
This register is a 6-bit read/write register. Its purpose is to store the number of the basic cycle for
Time -Triggered Transmissions. Its value is updated in different fashions depending if this module
is programmed to work as a potential time master or as a time slave. If this module is working as
(potential) time master, CCR is:
Incremented by one every time the cycle time (CYCTR) matches to Tx-Trigger Time of
Mailbox-30 or
Overwritten with the value contained in MSG_DATA_0[5:0] of Mailbox 31 when a valid
reference message is received.
If this module is working as a time slave, CCR is only overwritten with the value of
MSG_DATA_0[5:0] of Mailbox 31 when a valid reference message is received.
If CMAX = 3'111, CCR is always H'0000.
CCR (Address = H'08A)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
RRRRRRRRRRR/W R/W R/W R/W R/W R/W
CCR[5:0]
Bit:
Initial value:
R/W:
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