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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 147 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.6 Exceptions Triggered by Instructions
6.6.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, general illegal instructions, slot illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 6.10.
Table 6.10 Types of Exceptions Triggered by Instructions
Type Source Instruction Comment
Trap instruction TRAPA
Slot illegal
instructions
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
(including FPU instructions and
FPU-related CPU instructions in
FPU module standby state),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
General illegal
instructions
Undefined code anywhere
besides in a delay slot (including
FPU instructions and FPU-related
CPU instructions in FPU module
standby state)
Integer division
exceptions
Division by zero DIVU, DIVS
Negative maximum value (1) DIVS
FPU exceptions Starts when detecting invalid
operation exception defined by
IEEE754, division-by-zero
exception, overflow, underflow, or
inexact exception.
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FLOAT, FTRC,
FCNVDS, FCNVSD, FSQRT