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Section 6 Exception Handling
R01UH0134EJ0400 Rev. 4.00 Page 139 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
6.2.3 Power-On Reset
(1) Power-On Reset by Means of RES Pin
When the RES pin is driven low, this LSI enters the power-on reset state. To reliably reset this
LSI, the RES pin should be kept at the low level for the duration of the oscillation settling time at
power-on or when in software standby mode (when the clock is halted), or at least 20-tcyc when
the clock is running. In the power-on reset state, the internal state of the CPU and all the on-chip
peripheral module registers are initialized. See appendix A, Pin States, for the status of individual
pins during the power-on reset state.
In the power-on reset state, power-on reset exception handling starts when the RES pin is first
driven low for a fixed period and then returned to high. The CPU operates as follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000, the interrupt mask level bits (I3 to
I0) of the status register (SR) are initialized to H'F (B'1111), and the BO and CS bits are
initialized to 0. The BN bit in IBNR of the interrupt controller is also initialized to 0. FPSCR is
initialized to H'00040001
4. The values fetched from the exception handling vector table are set in the PC and SP, and the
program begins executing.
Be certain to always perform power-on reset processing when turning the system power on.
(2) Power-On Reset by Means of User Debugging Interface Reset Assert Command
When the user debugging interface reset assert command is set, this LSI enters the power-on reset
state. Power-on reset by means of the user debugging interface reset assert command is equivalent
to power-on reset by means of the RES pin. Setting the user debugging interface reset negate
command cancels the power-on reset state. The time required between the user debugging
interface reset assert command and the user debugging interface reset negate command is the same
as the time to keep the RES pin low to initiate a power-on reset. In the power-on reset state
generated by the user debugging interface reset assert command, setting the user debugging
interface reset negate command starts power-on reset exception handling. The CPU operates in the
same way as when a power-on reset was caused by the RES pin.