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Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00 Page 1363 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
3 to 0 UTST[3:0] 0000 R/W (1) When the host controller function is selected
These bits can be set after writing 1 to DRPD. This
module outputs waveforms when both DRPD and
UACT are set to 1. This module also performs high-
speed termination after the UTST bits are written to.
Procedure for setting the UTST bits
1. Power-on reset.
2. Start the clock supply (Set SCKE to 1 after
the crystal oscillation and the PLL for USB
are settled).
3. Set DCFM and DRPD to 1 (setting HSE to 1
is not required).
4. Set USBE to 1.
5. Set the UTST bits to the appropriate value
according to the test specifications.
6. Set the UACT bit to 1.
Procedure for modifying the UTST bits
1. (In the state after executing step 6 above)
Set UACT and USBE to 0.
2. Set USBE to 1.
3. Set the UTST bits to the appropriate value
according to the test specifications.
4. Set the UACT bit to 1.
When these bits are set to Test_SE0_NAK (1011),
this module does not output the SOF packet even
when 1 is set to UACT.
When these bits are set to Test_Force_Enable
(1101), this module outputs the SOF packet when 1
is set to UACT. In this test mode, this module does
not perform hardware control consequent to
detection of high-speed disconnection (detection of
the DTCH interrupt).
When setting the UTST bits, the PID bits for all the
pipes should be set to NAK.
To return to normal USB communication after a test
mode has been set and executed, a power-on reset
should be applied.