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Section 31 On-Chip RAM
Page 1674 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 31.6 Number of Cycles for Access to On-Chip High-Speed RAM from the ID Bus
Read/Write Ratio of I and B Number of Access (B) Cycles
Read 1:1 3
2:1 2
3:1 2
4:1 2
6:1 1
8:1 1
Write 1:1 2
2:1 2
3:1 2
4:1 2
6:1 1
8:1 1
Note: For the settable ratios of I to B, see section 5, Clock Pulse Generator.
On-chip large-capacity RAM: the number of cycles for access to read or write from any bus is
one cycle of B.