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Section 7 Interrupt Controller
Page 200 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
F
2 Icyc + 3 Bcyc + 1 Pcyc 1 Icyc + m1 + m2 + 2(m4)
m1 m2 m3
2 Icyc + 17(m4)
IRQ
RESBANK instruction
DEMMM MMMW
DEEMM
M
F
D
m4
m4
[Legend]
m1:
m2:
m3:
m4:
Vector address read
Saving of SR (stack)
Saving of PC (stack)
Restoration of banked registers
Interrupt acceptance
First instruction in interrupt
exception service routine
Instruction (instruction replacing
interrupt exception handling)
...
...
...
Figure 7.9 Example of Pipeline Operation when Interrupt is Accepted during RESBANK
Instruction Execution (Register Banking with Register Bank Overflow)