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Section 25 NAND Flash Memory Controller
Page 1308 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit Name
Initial
Value R/W Description
17 DREQ1EN 0 R/W FLECFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLECFIFO.
0: Disables the DMA transfer request issued from
FLECFIFO
1: Enables the DMA transfer request issued from
FLECFIFO
16 DREQ0EN 0 R/W FLDTFIFODMA Request Enable
Enables or disables the DMA transfer request issued
from FLDTFIFO.
0: Disables the DMA transfer request issued from the
FLDTFIFO
1: Enables the DMA transfer request issued from the
FLDTFIFO
15 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 ECERB 0 R/(W)* ECC Error
Indicates the result of ECC error detection. This bit is
set to 1 if an ECC error occurs while flash memory is
read in sector access mode.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no ECC error occurs (Latched ECC is
all 0.)
1: Indicates that an ECC error occurs