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Section 27 Video Display Controller 3
Page 1620 of 2108 R01UH0134EJ0400 Rev. 4.00
Sep 24, 2014
SH7262 Group, SH7264 Group
27.7.36 Timing Control Register 2 for Vertical Sync Signal for Video
(VIDEO_VSYNC_TIM2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
0000000000000000
RRRRRRRRRRRRRRRR
0000000000000000
RRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W
------
-
----------
- - - - - VIDEO_VSYNC_START2[9:0]
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Bit Bit Name
Initial
Value
R/W Description
31 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 0 VIDEO_VSYNC
_START2[9:0]
H'000 R/W These bits specify in number of lines the interval
between the reference vertical sync signal and the
point where the vertical sync signal (VSYNC) for
video is set to 1.