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SYSTEM
0BJECrS
STRUCl'URES
Peripheral
Subsystem
State
Field
-
The
organization
of
the
Peripheral
Subsystem
state
field
is
shown
belCM.
1
12
bits
lxlxxlxl
1 1
1
1--
write
sample
delay
!
1---
xack
delay
1
1-------
interrupt
inhibit
1-------------
reserved
The
write
sample
delay
field
and
the
xack
delay
field
program
the
characteristics
of
the
IP
conponent
interface
to
the
Peripheral
Subsystem.
See
the
iAPx 43203
VI..SI
Interface
Processor
Data
Sheet,
Order
Number
171874-001
for
details.
If
the
interrupt
inhibit
field
is
a 1
then
the
IP
will
inhibit
normal
function
complete
interrupts
but
will
continue
pass
all
other
interrupts
to
the
AP.
If
the
interrupt
inhibit
field
is
0
then
the
IP
will
report
successful
function
completions
with
interrupts.
IPC
State
Field
-
The IPC
state
field
is
used
to
indicate
that
the
processor
has
responded
to
an
interprocessor
conmunication
signal
and
signalled
the
associated
Peripheral
Subsystem
via
interrupt.
It
has
the
following
organization.
14
bits
lxlxl
1 1
1 1
--
local
IPC
response
1 1
---
global
IPC
response
1-----------
reserved
With
either
IPC
response
flag,
a
value
of
zero
indicates
that
00
such
response
has
occured
and a
value
of
one
indicates
that
such
a
response
has
occured.
A-13
•