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WINOOWS
BLOCK
MODE
CCNSIS'lENCY
CHEr!K
Since
the
byte
count
and
base
displacement
effectively
predefine
the
transfer
from
the
perspective
of
the
432
object,
the
IP
can perform
most
of
the
required
consistency
checks
when
the
window
is
opened.
The
only
checks
made
during
a
transfer
are
direction
and
byte
count.
BI.D:K
moE
OPERATICN
From
the
p::>int
of
view
of
the
Per
ipheral
Subsystem
bus,
a
block
transfer
proceeds
much
like
a randan
transfer,
except
that,
like
a
fast
menory,
the
IP
provides
much
better
response
time
in
block
mode. The
IP
acts
as
a
passive
agent
on
the
PS
bus,
all
block
transfer
activity
being
driven
by an
active
PS
processor
or
u.1A
controller.
When
an
address
reference
falls
within
window
D's
sub
range,
the
IP
accepts
or
supplies
a
byte
or
double-byte
according
to
the
type
of
PS
bus
cycle.
Note,
however,
that
in
block
mode,
IP
acknowledgement
of
a
write
operation
does
not
neccessarily
imply
that
the
data
has
actually
been
written
into
the
windowed
object.
The
IP
employs an
on-chip
first-in-first-out
(FIFO)
buffer
to
achieve
high
speed block
transfers
in
buffered
moae:--8ince
a
block
mode
transfer
is
predefined
b¥
window
D's
attributes,
the
IP
is
able
to
optimize
the
transfer
using
the
FIFO
hardware
assistance.
The
Interface
Processor
buffers
block
mode
transfers
to
improve
response
to
Peripheral
Subsystem
transfer
requests
and
to
reduce
its
utilization
of
the
432
processor
packet
bus.
In
a
block
read
operation,
the
Interface
Processor
pre-fetches
an
eight-~yte
block
of
data
from
the
windowed
object
in
one
432
processor
packet
rus
transaction.
It
holds
the
block
in
an
internal
buffer
and
supplies
bytes
or
double-bytes
from
the
buffer
as
requested
by
Peripheral
Subsystem
ooscycles.
When
the
buffer
has
enough
free
space,
the
IP
prefetches
another
block.
In
a
block
mode
write
operation,
the
IP
accepts
bytes
or
double-bytes
from
the
Peripheral
Subsystem bus and
buffers
them
internally.
When
the
buffer
accumulates more
than
eight
bytes,
the
IP
post-stores
an
eight-byte
block
in
the
windowed
object
in
a
single
processor
packet
bus
operation.
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