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iAPX
432
Interface
Processor
Architecture
Reference
Manual
1-5.
SUPPLEMENTARY
INTERFACE
ProcESSOR
FACILITIES
The
preceding
sections
have
described
the
Interface
Processor
as
it
is
used
most
of
the
time.
The
IP
provides
two
additional
capabilities
which
are
typically
used
less
frequently,
often
only
in
exceptional
circumstances.
These
are
physical
reference
nnde and
interconnect
access.
PHYSICAL
REFERENCE
r-DDE
An
IP
oormally
operates
in
logical
reference
nnde.
This
nnde
is
characterized
by
its
object-oriented
addressing
and
protection
system.
When
an
IP
running
in
logical
node opens a window,
it
utilizes
an
object
selector
to
specify
a
particular
432
data
segment.
There
are
times
when
logical
referencing
is
impossible
because
the
objects
used
by
the
hardware
to
perform
logical-to-physical
address
development
are
absent
(or,
less
likely,
are
damaged).
In
these
situations
the
IP
can
be
used
in
physical
reference
nnde.
An
IP
which
is
operating
in
physical
reference
node
circumvents
the
protection
mechanisms
of
the
432
system.
No
distinction
is
made
between
data
segments and
access
segments
in
physical
reference
m<rle.
The
IP
provides
a
reduced
set
of
functions
in
this
mode.
Windows
map
directly
onto
contiguous
segments
of
432
physical
memory
(rather
than
obj
ect
structures
in
432 memory). The
IP
controller
selects
a segment
by
specifying
a
24-bit
physical
address
when
it
establishes
a window. The
IP
interprets
subsequent
subrange
references
as
l6-bit
displacements
from
the
segment's
base
address.
This
s~le
base-plus-displacement
addressing
is
s~ilar
to
traditional
computer
addressing
techniques.
Physical
reference
mode
is
most
often
employed
during
system
initialization
to
load
~es
of
objects
from a
Peripheral
Subsystem
into
432 memory. Once
the
required
objects
are
available,
processors
can
begin
normal
logical
reference
node
operations.
lDgical
mode
cannot
be
used
until
the
obj
ect
tables
required
for
logical-to-physical
address
translation
have
been
constructed
and
loaded
into
432 memory.
INTEocx::NNECr
ACCESS
In
addition
to
merrory,
the
iAPX
432
architecture
defines
a
second,
independent
address
space
called
the
processor-memory
interconnect
address
space.
The
interconnect
address
space
allows
interconnect
obj
ects
to
be
maintained
which
may
contain
one
or
more
interconnect
registers.
Interconnect
registers
are
double
l:¥te
quantities
which
are
aligned
on
double
byte
boundaries.
With
the
exception
of
a few
reserved
addresses,
the
definition
and
use
of
interconnect
locations
is
not
pre-defined
for
the
IP.
A{:pendix E
of
this
manual
suggests
how
the
interconnect
may
be
utilized
during
the
initialization
of
variable-configuration
systems.
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