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The
IP
(like
a
GOP)
requires
two
register
interconnect
space
to
be
defined
for
any system:
o
the
processor
ID
register
(interconnect
o
the
interprocessor
communication
(interconnect
address
2)
KEY
CONCEPTS
locations
address
0)
(IPC)
in
the
register
The remainder
of
the
interconnect
address
space
may
be
used
to
store
or
acquire
other
infoonation
such
as
configuration
parameters,
error
logging
registers,
and
other
application-specific
quantities.
Window
1
is
software-switchable
between
the
memory
and
the
interconnect
spaces.
In
logical
reference
node,
the
interconnect
space
is
addressed
in
the
same
object-oriented
manner
as
the
memory
space,
with
the
IP
automatically
performing
the
logical-to-physical
address
developnent.
'lb
access
the
interconnect
space,
the
I/O
controller
must
specify
an
object
selector
for
an
interconnect
obj
ect
which exposes a segment
of
the
interconnect
space
to
the
IP.
The
normal
window
addressing
scheme
is
then
used
to
locate
individual
interconnect
registers
within
the
object.
Switching
window
1
to
interconnect
access
mode
gives
the
IP
access
to
interconnect
objects.
This
operation
is
equivalent
to
the
MOVE
TO
INTE~
and MJVE
FRG1
INTE~
~rators
of
the
GOP.
In
physical
reference
mode,
the
interconnect
space
is
addressed
as
a
linear
array
of
even-addressed,
double-byte,.
interconnect
registers.
As
with
physical
reference
mode
memory
accesses,
the
swi
tchable
window
is
set
up
with
a
24-bi
t
physical
base
address.
Peripheral
subsystem
references
to
the
corresponding
subrange
are
likewise
interpreted
by
the
IP
as
l6-bit
displacements
from
the
base
address
to
individual
interconnect
registers.
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