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Intel® Solid-State Drive DC P3700 Series
May 2015 Product Specification
330566-009US 21
Pin
Name
Description
Pin
Name
Description
E17
PETp3
Transmitter differential pair, Lane 3
E18
PETn3
Transmitter differential pair, Lane 3
E19
GND
Ground
E20
PERn3
Receiver differential pair, Lane 3
E21
PERp3
Receiver differential pair, Lane 3
E22
GND
Ground
E23
SMCLK
SMBus clock
E24
SMDAT
SMBus data
E25
DualPortEn_N
Dual port enable
NOTES:
SMCLK and SMDAT routes to an internal EEPROM which contains Vital Product Data (VPD).
PRSNT_N is kept open by the P3700 Series.
IfDet_N is grounded by P3700 Series.
DualPortEn_N pin should be left un-connected or un-driven by the system to enable single port operation with
all 4 lanes. If un-connected, P3700 Series will pull it high. However, if the pin is asserted by the system (driven
low by storage backplane), then P3700 Series will be configured as x2 lanes
Transmit differential pair lanes have 220 nF of AC coupling capacitance.
P11 is used for activity. When idle, logic level is low (LED Solid On). During IO activity and formatting,
pin toggles 250msec high, 250msec low signal.
P3700 Series only uses REFCLK0+ and REFCLK0- as reference clock pair.
P3700 Series only uses PERST0# as a fundamental reset.
3.3Vaux is only needed during SMBUS access to the VPDROM.