7.4.2.2DSPModuleClockOff
7.53.3VI/OPowerDown
7.6VideoDACPowerDown
3.3VI/OPowerDown
IntheclockDisablestate,theDSP’smoduleclockisdisabled,whileDSPresetremainsde-asserted.This
stateistypicallyusedtodisabletheDSPclocktosavepower.AsmentionedinSection7.4.2,theDSP
cannotputitselfinDisablestate.Anexternalhostisresponsibleforperformingthistask.Forexample,it
canbeanexternalhostinterfacingthroughtheHPIorPCIperipheral.
•Host:NotifytheDSPtoprepareforpower-down.
•DSP:DrainallexistingoperationsandensuretherearenoaccessestotheC64x+megamoduleprior
toDSPpower-down.
–ProgramthePSCtodisableallmasterperipherals(excepttheHost)thatarecapableofinitiating
transferstotheC64x+Megamodule.
–CheckEDMAtransferstatustoensurethereisnooutstandingEDMAtransfersthatcanaccessthe
C64x+Megamodule.
•DSP:Prepareforpower-down.
–SetPDCCMDto00015555h.PDCCMDisacontrolregisterintheDSPpower-downcontroller
module.
Note:ThisregistercanonlybewrittenwhiletheDSPisinsupervisormode.
–EnableoneoftheinterruptsthatthehostwouldliketousetowaketheDSPintheDSPclock-on
sequence.
–ExecutetheIDLEinstruction.IDLEisaprograminstructionintheC64x+CPUinstructionset.When
theCPUexecutesIDLE,thePDCisnotifiedandinitiatesDSPpower-downaccordingtothebits
thatyousetinthePDCCMD(01810000h)register.SeetheTMS320C64x+DSPMegamodule
ReferenceGuide(SPRU871)formoreinformationonthePDCandtheIDLEinstruction.
•Host:DisabletheDSPclock.
–WaitfortheGOSTAT[0]bitinPTSTATtoclearto0.Youmustwaitforthepowerdomaintofinish
anypreviouslyinitiatedtransitionsbeforeinitiatinganewtransition.
–SettheNEXTbitinMDCTL39to2htopreparetheDSPmoduleforadisabletransition.
–SettheGO[0]bitinPTCMDto1toinitiatethestatetransition.
–WaitfortheGOSTAT[0]bitinPTSTATtoclearto0.Thedomainisonlysafelyinthenewstate
aftertheGOSTAT[0]bitisclearedto0.
–WaitfortheSTATEbitinMDSTAT39tochangeto2h.Themoduleisonlysafelyinthenewstate
aftertheSTATEbitinMDSTAT39changestoreflectthenewstate.
The3.3VI/Odriversarefabricatedoutof1.8VtransistorswithdesigntechniquesthatrequireaDCbias
current.TheseI/Ocellshaveapower-downmodethatturnsofftheDCcurrent.TheVDD3P3V_PWDN
registeroftheSystemModulecontrolsthisstandbymode.Refertothedevice-specificdatamanualfor
moredetailsontheVDD3P3V_PWDNregister.
TheDM643xDMPvideoprocessingbackend(VPBE)includesfourvideodigital-to-analogconverters
(DACs)todriveanalogtelevisiondisplays.TheVideoEncoder(VENC)moduleoftheVPBEincludes
registersforenabling/disablingtheDACs.YoucanusetheVIEbitinVMODtoforcetheanalogoutputof
the4DACstoalowlevel,regardlessofthevideosignal.Furthermore,youcanusetheDAPD[3:0]bitsin
DACTSTtodisableeachDACindependently.SeetheTMS320DM643xDMPVideoProcessingBackEnd
(VPBE)User'sGuide(SPRU952)forregisterdescriptionsandmoredetailedinformationonDAC
power-down.
SPRU978E–March2008PowerManagement81
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