2.1Introduction
2.2TMS320C64x+CPU
Introduction
TheC64x+Megamodule(Figure2-1)consistsofthefollowingcomponents:
•TMS320C64x+CPU
•Internalmemorycontrollers:
–Level-1programmemorycontroller(L1Pcontroller)
–Level-1datamemorycontroller(L1Dcontroller)
–Level-2unifiedmemorycontroller(L2controller)
–Externalmemorycontroller(EMC)
–Internaldirectmemoryaccess(IDMA)controller
•Internalperipherals
–Interruptcontroller(INTC)
–Power-downcontroller(PDC)
TheC64x+MegamoduleincludestheC64x+CPU.TheC64x+CPUisamemberoftheTMS320C6000™
generationofdevices.TheC6000™devicesexecuteuptoeight32-bitinstructionspercycle.TheCPU
consistsof64general-purpose32-bitregistersandeightfunctionalunits.Theeightfunctionalunitscontain
twomultipliersandsixALUs.FormoreinformationontheCPU,seetheTMS320C64x/C64x+DSPCPU
andInstructionSetReferenceGuide(SPRU732).
FeaturesoftheC6000devicesinclude:
•AdvancedVLIWCPUwitheightfunctionalunits,includingtwomultipliersandsixarithmeticunits
–ExecutesuptoeightinstructionspercycleforuptotentimestheperformanceoftypicalDSPs
–AllowsdesignerstodevelophighlyeffectiveRISC-likecodeforrapiddevelopmenttime
•Instructionpacking
–Givescode-sizeequivalenceforeightinstructionsthatexecuteseriallyorinparallel
–Reducescodesize,programfetches,andpowerconsumption
•Conditionalexecutionofmostinstructions
–Reducescostlybranching
–Increasesparallelismforhighersustainedperformance
•Efficientcodeexecutiononindependentfunctionalunits
–Industry'smostefficientCcompileronDSPbenchmarksuite
–Industry'sfirstassemblyoptimizerforrapiddevelopmentandimprovedparallelization
•8/16/32-bitdatasupport,providingefficientmemorysupportforavarietyofapplications
•40-bitarithmeticoptionsaddextraprecisionforvocodersandothercomputationallyintensive
applications
•Saturationandnormalizationprovidesupportforkeyarithmeticoperations
•Fieldmanipulationandinstructionextract,set,clear,andbitcountingsupportacommonoperation
foundincontrolanddatamanipulationapplications
TheC64x+devicesincludethefollowingadditionalfeatures:
•Eachmultipliercanperformtwo16×16-bitorfour8×8-bitmultiplieseveryclockcycle
•Quad8-bitanddual16-bitinstructionsetextensionswithdataflowsupport
•Supportfornonaligned32-bit(word)and64-bit(doubleword)memoryaccesses
•Specialcommunication-specificinstructionstoaddresscommonoperationsinerror-correctingcodes
•Bitcountandrotatehardwareextendssupportforbit-levelalgorithms
•Compactinstructions:commoninstructions(AND,ADD,LD,MPY)have16-bitversionstoreducecode
size
16TMS320C64x+MegamoduleSPRU978E–March2008
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