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16-BIT TIMER 1(0,1) S3C84E5/C84E9/P84E9
12-6
BLOCK DIAGRAM
fxx/1
f xx/64
f xx/8
V
S
S
T1CK
f xx/256
f xx/1024
NOTES:
1. When PWM mode, match signal cannot clear counter.
2. Pending bit is located at TINTPND register.
Clear
Match
T1CON.7-.5
T1CON.0
Pending
T1CON.2
Overflow
T1OVF
T1CAP
T1OUT(T1PWM)
TINTPND
T1CON.4.3
T1CON.4-.3
Data Bus
8
Data Bus
8
M
U
X
M
U
X
16-bit Up-Counter
(Read Only)
16-bit Comparator
16-bit Timer Buffer
16-bit Timer Data Register
(T1DATAH/L)
M
U
X
T1CON.1
Pending
T1INT
TINTPND
M
U
X
Figure 12-3. Timer 1(0,1) Functional Block Diagram