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DM9161B
10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
37 Final
Version: DM9161B-12-DS-F01
January 31, 2008
9.4.3 Power On Reset Timing
RESET#
Strap pins
T2
T1
pwrst#.vsd
Symbol Parameter Min. Typ. Max. Unit Conditions
T1 RESET# Low Period 1 - - ms -
T2 Strap pin hold time with RESET# 40 - - ns -
9.4.4 MDC/MDIO Timing
Symbol Parameter Min. Typ.
Max. Unit Conditions
t0 MDC Cycle Time 80 - - ns
t1
MDIO Setup Before MDC 10 - - ns When OUTPUT By STA
t2
MDIO Hold After MDC 10 - - ns When OUTPUT By STA
t3
MDC To MDIO Output Delay 0 - 300 ns When OUTPUT By DM9161B
9.4.5 MDIO Timing When OUTPUT by STA
MDC
t
1
MDIO
10ns
(Min)
t
2
10ns
(Min)
t0
9.4.6 MDIO Timing When OUTPUT by DM9161B
MDC
t
3
MDIO
0 - 300 ns
t0