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CHAPTER 5: Technical Description
5. Technical Description
5.1 Interrupts
A good analogy of a PC interrupt is a telephone ringing. The phone bell is a
request for us to stop what we are currently doing and take up another task (speak
to the person on the other end of the line). This is the same process the PC uses to
alert the CPU that a task must be performed. The CPU, upon receiving an
interrupt, makes a record of what the processor was doing at the time and stores
this information on the “stack”; this allows the processor to resume its predefined
duties after the interrupt is handled, exactly where it left off. Every main sub-system
in the PC has its own interrupt, frequently called an IRQ (short for Interrupt
ReQuest).
5.2 Why Use an ISP?
The Interrupt Status Port (ISP) is a read-only 8-bit register that sets a
corresponding bit when an interrupt is pending. Port 1 interrupt line corresponds
with Bit D0 of the status port, Port 2 with D1, etc. The use of this port means that
the software designer now only has to poll a single port to determine if an
interrupt is pending.
The ISP is at Base+7 on each port (example: Base=280 hex, Status Port=287,
28F...etc.). The Adapter will allow any one of the available locations to be read
to obtain the value in the status register. Both status ports on the Adapter are
identical, so either one can be read. Example: This indicates that Channel 2 has
an interrupt pending.
Bit Position: 76543210
Value Read: 00000010