2.14InterruptSupport
2.15DMAEventSupport
2.16PowerManagement
PLLC2
CLKSTOP_REQ
DDR
PSC
CLKSTOP_ACK
MODCLK
MODRST
LRST
DDR2
memory
controller
VCLKSTOP_REQ
VCLKSTOP_ACK
VCLK
VRST
VCTL_RST
X2_CLK
/2
SYSCLK2
PLL2_SYSCLK1
PeripheralArchitecture
TheDDR2memorycontrollersupportstwoaddressingmodes,linearincrementingandcachelinewrap.
Uponreceiptofanaccessrequestforanunsupportedaddressingmode,theDDR2memorycontroller
generatesaninterruptbysettingtheLTbitintheinterruptrawregister(IRR).TheDDR2memory
controllerwillthentreattherequestasalinearincrementingrequest.
ThisinterruptiscalledthelinetrapinterruptandistheonlyinterrupttheDDR2memorycontroller
supports.Itisanactive-highinterruptandisenabledbytheLTMSETbitintheinterruptmasksetregister
(IMSR).ThisinterruptismappedtoboththeDSPandtheARMandisnotmultiplexedwithother
interrupts.
TheDDR2memorycontrollerisaDMAslaveperipheralandthereforedoesnotgenerateDMAevents.
DatareadandwriterequestsmaybemadedirectlybymastersandbytheDMA.
PowerdissipationfromtheDDR2memorycontrollermaybemanagedbytwomethods:
•Self-refreshmode(seeSection2.10)
•Gatinginputclockstothemoduleoff
GatinginputclocksofftotheDDR2memorycontrollerachieveshigherpowersavingswhencomparedto
thepowersavingsofself-refreshmode.TheinputclocksareturnedoffoutsideoftheDDR2memory
controllerthroughtheuseofthePowerandSleepController(PSC)andthePLLcontroller2(PLLC2).
Figure16showstheconnectionsbetweentheDDR2memorycontroller,PSC,andPLLC2.Fordetailed
informationonpowermanagementproceduresusingthePSC,seetheTMS320DM643xDMPDSP
SubsystemReferenceGuide(SPRU978).
Beforegatingclocksoff,theDDR2memorycontrollermustplacetheDDR2SDRAMmemoryin
self-refreshmodebysettingtheSRbitintheSDRAMrefreshcontrolregister(SDRCR)to1.Iftheexternal
memoryrequiresacontinuousclock,theDDR2memorycontrollerclockprovidedbyPLLC2mustnotbe
turnedoffbecausethismayresultindatacorruption.Seethefollowingsubsectionsfortheproper
procedurestofollowwhenstoppingtheDDR2memorycontrollerclocks.Oncetheclocksarestopped,to
re-enabletheclocksfollowtheclockstopprocedureineachrespectivesubsectioninreverseorder.
Figure16.DDR2MemoryControllerPowerSleepControllerDiagram
DDR2MemoryController 34SPRU986B–November2007
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