Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M59
M58
M55
M57
M56
M54M53
CLKX
FSX
DX
DR
M62
TMS320DM355
DigitalMediaSystem-on-Chip(DMSoC)
SPRS463A–SEPTEMBER2007–REVISEDSEPTEMBER2007
Table5-43.ASPasSPITimingRequirements
CLKSTP=11b,CLKXP=1(seeFigure5-45)
MASTER
NO.UNIT
MINMAX
M58t
su(DRV-CKXL)
Setuptime,DRvalidbeforeCLKXlow11ns
M59t
h(CKXL-DRV)
Holdtime,DRvalidafterCLKXlow0ns
Table5-44.ASPasSPISwitchingCharacteristics
(1)(2)
CLKSTP=11b,CLKXP=1(seeFigure5-45)
MASTER
NO.PARAMETERUNIT
MINMAX
38.5or
M62tc(CKX)Cycletime,CLKXns
2P
(3)(3)
M53t
d(CKXH-FXH)
Delaytime,CLKXhightoFSXhigh
(4)
D–1D+3ns
M54t
d(FXL-CKXL)
Delaytime,FSXlowtoCLKXlow
(5)
T–2T+2ns
M55t
d(CKXL-DXV)
Delaytime,CLKXlowtoDXvalid–26ns
Disabletime,DXhighimpedancefollowinglastdatabitfrom
M56t
dis(CKXH-DXHZ)
–3+3ns
CLKXhigh
M57t
d(FXL-DXV)
Delaytime,FSXlowtoDXvalidC–1C+10ns
(1)P=(1/SYSCLK2),whereSYSCLK2isanoutputclockofPLLC1(seeSection3.5).
(2)T=CLKXperiod=(1+CLKGDV)×P
C=CLKXlowpulsewidth=T/2whenCLKGDVisoddorzeroand=(CLKGDV/2)×PwhenCLKGDViseven
D=CLKXhighpulsewidth=T/2whenCLKGDVisoddorzeroand=(CLKGDV/2+1)×PwhenCLKGDViseven
(3)Usewhichevervalueisgreater.
(4)FSRP=FSXP=1.AsaSPImaster,FSXisinvertedtoprovideactive-lowslave-enableoutput.
CLKXM=FSXM=1,CLKRM=FSRM=0formasterASP
(5)FSXshouldbelowbeforetherisingedgeofclocktoenableslavedevicesandthenbeginaSPItransferattherisingedgeofthemaster
clock(CLKX).
Figure5-45.ASPasSPI:CLKSTP=11b,CLKXP=1
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