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TMS320C6712D
FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR
SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
EMIF device speed
The maximum EMIF speed on the device is 100 MHz. TI recommends utilizing I/O buffer information
specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given
board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using
IBIS Models for Timing Analysis application report (literature number SPRA839).
For ease of design evaluation, Table 33 contains IBIS simulation results showing the maximum EMIF-SDRAM
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be
performed to verify that all AC timings are met for the specified board layout. Other configurations are also
possible, but again, timing analysis must be done to verify proper AC timings.
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
Table 33. Example Boards and Maximum EMIF Speed
BOARD CONFIGURATION
MAXIMUM ACHIEVABLE
TYPE
EMIF INTERFACE
COMPONENTS
BOARD TRACE
SDRAM SPEED GRADE
MAXIMUM ACHIEVABLE
EMIF-SDRAM
INTERFACE SPEED
143 MHz 32-bit SDRAM (−7) 100 MHz
1-Load
One bank of one
1 to 3-inch traces with proper
termination resistors;
166 MHz 32-bit SDRAM (−6)
For short traces, SDRAM data
output hold time on these
1-Load
Short Traces
One bank of one
32-Bit SDRAM
1 to 3-inch traces with proper
termination resistors;
Trace impedance ~ 50 Ω
183 MHz 32-bit SDRAM (−55)
output hold time on these
SDRAM speed grades cannot
meet EMIF input hold time
Trace impedance ~ 50 Ω
200 MHz 32-bit SDRAM (−5)
meet EMIF input hold time
requirement (see NOTE 1).
125 MHz 16-bit SDRAM (−8E) 100 MHz
2-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
2-Loads
Short Traces
One bank of two
16-Bit SDRAMs
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
16-Bit SDRAMs
termination resistors;
Trace impedance ~ 78
Ω
167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6) 100 MHz
125 MHz 16-bit SDRAM (−8E)
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
3-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
3-Loads
Short Traces
One bank of two
32-Bit SDRAMs
One bank of buffer
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
32-Bit SDRAMs
One bank of buffer
termination resistors;
Trace impedance ~ 78
Ω
167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6)
For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
One bank of one
143 MHz 32-bit SDRAM (−7) 83 MHz
One bank of one
32-Bit SDRAM
166 MHz 32-bit SDRAM (−6) 83 MHz
3-Loads
Long Traces
32-Bit SDRAM
One bank of one
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
183 MHz 32-bit SDRAM (−55) 83 MHz
3-Loads
Long Traces
One bank of one
32-Bit SBSRAM
One bank of buffer
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
200 MHz 32-bit SDRAM (−5)
SDRAM data output hold time
cannot meet EMIF input hold
requirement (see NOTE 1).
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing
requirements can be met for the particular system.