- 12 -
Unbuffered SODIMM datasheet DDR3 SDRAM
Rev. 1.0
10.3 AC and DC Logic Input Levels for Differential Signals
10.3.1 Differential Signals Definition
Figure 2. Definition of differential ac-swing and "time above ac level" tDVAC
10.3.2 Differential Swing Requirement for Clock (CK-CK) and Strobe (DQS-DQS)
NOTE :
1. Used to define a differential signal slew-rate.
2. for CK - CK
use V
IH
/V
IL
(AC) of ADD/CMD and V
REFCA
; for DQS - DQS use V
IH
/V
IL
(AC) of DQs and V
REFDQ
; if a reduced ac-high or ac-low level is used for a signal group,
then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK
, DQS, DQS need to be within the respective limits (V
IH
(DC) max, V
IL
(DC)min) for single-ended sig-
nals as well as the limitations for overshoot and undershoot. Refer to "overshoot and Undershoot Specification"
[ Table 3 ] Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS.
Symbol Parameter
DDR3-800/1066/1333/1600
unit NOTE
min max
V
IHdiff
differential input high +0.2 NOTE 3 V 1
V
ILdiff
differential input low NOTE 3 -0.2 V 1
V
IHdiff
(AC)
differential input high ac
2 x (V
IH
(AC) - V
REF
)
NOTE 3 V 2
V
ILdiff
(AC)
differential input low ac NOTE 3
2 x (V
IL
(AC) - V
REF
)
V2
Slew Rate [V/ns]
tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 350mV tDVAC [ps] @ |V
IH/Ldiff
(AC)| = 300mV
min max min max
> 4.0 75 - 175 -
4.0 57 - 170 -
3.0 50 - 167 -
2.0 38 - 163 -
1.8 34 - 162 -
1.6 29 - 161 -
1.4 22 - 159 -
1.2 13 - 155 -
1.0 0 - 150 -
< 1.0 0 - 150 -
0.0
tDVAC
V
IH
.DIFF.MIN
half cycle
Differential Input Voltage (i.e. DQS-DQS, CK-CK)
time
tDVAC
V
IH
.DIFF.AC.MIN
V
IL
.DIFF.MAX
V
IL
.DIFF.AC.MAX
