Intel® Solid-State Drive DC S3500
Product Specification December 2013
18 328860-003US
4.3 Connector Pin Signal Definitions
Table 15. Serial ATA Connector Pin Signal Definitions—2.5-inch and 1.8-inch Form
Pin Function Definition
st
Differential signal pair A
st
Differential signal pair B
st
Note: Key and spacing separate signal and power segments.
4.4 Power Pin Signal Definitions
Table 16. Serial ATA Power Pin Definitions—2.5-inch Form Factors
Pin
1
Function Definition Mating Order
2
2
2
(3.3 V Power; pre-charge)
nd
3,4
st
3
st
3
st
3,5
st
3,5
nd
3,5
nd
3
st
6
Device Activity Signal/Disable Staggered Spin-up
nd
3,4
st
7
st
7
nd
7
nd
Notes:
1. All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.
2. Pins P1, P2 and P3 are connected together, although they are not connected internally to the device. The host may put 3.3 V on
these pins.
3. The mating sequence is:
• ground pins P4-P6, P10, P12 and the 5V power pin P7
• signal pins and the rest of the 5V power pins P8-P9
4. Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to
discharge ESD in a suitably configured backplane connector.
5. Power pins P7, P8, and P9 are internally connected to one another within the device.
6. The host may ground P11 if it is not used for Device Activity Signal (DAS).
7. Pins P13, P14 and P15 are internally connected to one another within the device. The host may put 12 V on these pins.
